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Digital Circuit Logic and Design — Major (End Semester) 2025 question paper

MMMUT Computer Science and Engineering previous year question paper for Digital Circuit Logic and Design (BCS-211), semester 3, Major (End Semester) 2025. All 18 questions are listed below, each with a written answer on Nexsus.

Paper details

  • Subject: Digital Circuit Logic and Design (BCS-211)
  • Branch: Computer Science and Engineering
  • Semester: 3
  • Exam: Major (End Semester) 2025
  • Questions: 18

Questions asked in Digital Circuit Logic and Design Major (End Semester) 2025

  1. Q1(a). Perform: (11100)_2 - (11011)_2 using 2's complement. [2 marks]
  2. Q1(b). (a) For a data word of length m = 32, determine the minimum number of parity bits r required for a Hamming single-error-correcting code. Show the inequality used and the final value of r. (b) Using even parity and standard Hamming placement (parity bits at positions 1,2,4,8,...), generate the Hamming codeword for the 5-bit data 11011. Show parity positions and the final 9-bit codeword. [2 marks]
  3. Q1(c). Consider the following four-variable Boolean function in sum-of-products form F (b_3, b_2, b_1, b_0) = Σ(0, 2, 4, 8, 10, 11, 12). The value of the function is computed by considering b_3 b_2 b_1 b_0 as a 4-bit binary number, where b_3 denotes the most significant bit and b_0 denotes the least significant bit. Note that there are no don't-care terms. Find the minimized Boolean expression for F. [2 marks]
  4. Q1(d). Realize a Full Adder using only NAND gates. (Only circuit diagram required) [2 marks]
  5. Q1(e). A certain stage in a CLA adder asserts G = 0, indicating no intrinsic carry generation, but asserts P = 1, indicating full carry propagation capability. Using the CLA recursive carry formula, determine how the incoming carry affects the outgoing carry. [2 marks]
  6. Q1(f). If x and y are two decimal digits and (0.1101)_2 = (0.8xy5)_10, the decimal value of x + y is [2 marks]
  7. Q1(g). Prepare a truth table that represents the behavior of a full subtractor. [2 marks]
  8. Q2(a). A Boolean digital circuit is composed using two 4-input multiplexers (M1 and M2) and one 2-input multiplexer (M3) as shown in the figure. X0-X7 are the inputs of the multiplexers M1 and M2 and could be connected to either 0 or 1. The select lines of the multiplexers are connected to Boolean variables A, B and C as shown. Find the values of X0-X7 which will realise the values of the Boolean… [2 marks]
  9. Q2(b). Construct the excitation table mapping the present state Q and desired input D to the required J and K. Derive the minimal Boolean expressions for J and K, draw the logic diagram (gates only), and prove algebraically that the implemented circuit realizes Q+ = D. Here D, J-K refers to flipflop. [5 marks]
  10. Q2(c). Using only one 8:1 multiplexer, realize the Boolean function without using any additional logic gates. F(A,B,C,D) = Σm(0,1,2,5,7,8,10,14). Determine which variables will be used as select inputs, create the input mapping table, and draw the complete implementation diagram. [5 marks]
  11. Q3(a). The partial implementation of a two-bit counter using the T flip-flops following the sequence 0-2-3-1-0, as shown here: [Circuit diagram showing T flip-flops and XOR gate]. For completing the circuit, what should be the expression for X in terms of Q1 and Q2? [5 marks]
  12. Q3(b). Design a synchronous counter to go through the following states: 1, 4, 2, 3, 1, 4, 2, 3, 1, 4 [5 marks]
  13. Q3(c). Design a synchronous up-down binary counter (3-bit) using T flip-flops. Prepare the state transition table for both counting directions, derive minimized Boolean expressions for the flip-flop excitation inputs, and implement the corresponding logic diagram. [5 marks]
  14. Q4(a). The shift register shown in Fig. is initially loaded with the bit pattern 1010. Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position. After how many clock pulses will the content of the shift register become 1100? [Diagram shows a 4-bit… [5 marks]
  15. QQ1. Attempt any five parts of the following (Units I and II)
  16. QQ2. Attempt any two parts of the following. (Unit III only)
  17. QQ3. Attempt any two parts of the following. (Unit III only)
  18. QQ4. Attempt any two parts of the following. (Unit IV only)